The present invention relates to a semiconductor memory device, and more particularly, to an address control circuit employed in a semiconductor memory device.
Dynamic random access memory (DRAM) devices are usually operated on using typical signal paths such as a row address path, a column address path and a data path. Usually on the row address path, there are operations that extract a row address from an address supplied externally, select a word line by the row address, and amplify data of a memory cell, which is coupled to the selected word line, by a sense amplifier. Usually on the column address path, there are operations for extracting a column address from an address that is supplied externally by a column address control circuit (hereinafter, referred to as ‘column address control operation’), decoding the column address, and selecting a memory cell by an output enable signal that is selectively activated. Usually on the data path, there are operations for outputting data through bit lines to an external system in response to a selected output enable signal or for storing external data in a memory cell through a bit line.
In general semiconductor memory devices, pads through which addresses, commands and data are input and output are generally placed at the centers of chips of the semiconductor memory devices. But, in other semiconductor memory devices for mobile apparatuses, pads are disposed along the edges of the chips thereof. For example, while pads receiving an address and a command are placed at one edge of a semiconductor memory device chip, pads through which data are input/output are placed at the other edge of the chip.
FIG. 1 shows a semiconductor memory device having a general column address control circuit.
In the semiconductor memory device of FIG. 1, a command address input circuit 100, which includes receiving pads that receive an address and a command, is placed at the opposite edge region of a data input/output circuit 101, which includes I/O pads through which data are input/output, interposed by a memory cell array of banks BANK1˜BANK8. The edge region where the command address input circuit 100 is placed also includes a column address control circuit 102 that functions for column address control operations to extract a column address AY from an address A provided from the command address input circuit 100.
With this structure of the semiconductor memory device, in a read operation mode for the first bank BANK1, the column address AY generated from the column address control circuit 102 is used to select a first memory cell C1 through a first column address path CAP1 and then data is output from the first memory cell C1 to the data input/output circuit 101 by way of a first data path DP1. In a read operation mode for the eighth bank BANK8, the column address AY generated from the column address control circuit 102 is used to select a second memory cell C2 through a second column address path CAP2 and then data is output from the second memory cell C2 to the data input/output circuit 101 by way of a second data path DP2. In the read operation mode, the column address path is the same as the data path in the progress direction.
Meantime, in a write operation mode for the first bank BANK1, the column address AY generated from the column address control circuit 102 is used to select the first memory cell C1 through the first column address path CAP1 and then data DIN supplied into the data input/output circuit 101 is stored in the first memory cell C1 by way of a third data path DP3. During this operation, there is a skew between transmission times of the column address AY and the input data DIN because the first column address path CAP1 is shorter than the third data path DP3.
Further, in a write operation mode for the eighth bank BANK8, the column address AY generated from the column address control circuit 102 is used to select the second memory cell C2 through the second column address path CAP2 and then data DIN supplied into the data input/output circuit 101 is stored in the second memory cell C2 by way of a fourth data path DP4. During this operation, there is a skew between transmission times of the column address AY and the input data DIN because the fourth data path DP4 is shorter than the second column address path CAP3.